Computer systems include a number of components and elements, which are typically coupled via a bus or interconnect. Previously, input/output (IO) devices were coupled together through a conventional multi-drop parallel bus architecture referred to as Peripheral Component Interconnect (PCI). More recently, a new generation of an IO bus referred to as PCI-Express (PCIe) has been used to facilitate faster interconnection between devices having a serial physical layer communication protocol.
A PCIe architecture includes a layered protocol to communicate between devices. As an example, a physical layer, link layer, and transaction layer form a PCIe protocol stack. The PCIe link is built around dedicated unidirectional pairs of serial point-to-point connections referred to as a lane. A link between devices includes some number of lanes, such as one, two, sixteen, thirty-two, and so-on. The current PCIe specification, PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007), is available at http://www.pcisig.com/specifications/pciexpress/.
A physical layer can transmit (or receive) three types of link traffic: ordered sets, data link layer packets (DLLPs), and transaction layer packets (TLPs). Local link traffic, which includes ordered sets and DLLPs, is not forwarded and carries no routing information. In contrast, TLPs can pass from link to link, using routing information contained in a packet header. Specifically, each TLP contains a three or four double word (DW) (12 or 16 byte) header. Included in the 3DW or 3DW header are, inter alia, two fields: type and format (Fmt) that define the format of the remainder of the header and the routing method to be used on the entire TLP as it moves between devices in a PCIe system. While the header provides needed information, its format is fixed and prevents flexibility to provide additional information by way of the header.